[Verilog HDL] FSM Test Module

복잡한 design module과는 다르게 굉장히 심플합니다. ㅋㅋㅋ
다들 해보시길 ㅋㅋㅋ

결과:

소스:
module test_FSM; reg Clock, Rst, Brake, Acc; wire [1:0]Speed; integer i; FSM_CAR_SPEED_CNTL fsm( Clock, Rst, Brake, Acc, Speed ); initial begin Clock = 0; Rst = 0; Brake = 0; Acc = 0; #5 Rst = 1; forever #5 Clock = ~Clock; end initial begin for( i=0; i<8; i=i+1 ) #30 Acc = ~Acc; for( i=0; i<8; i=i+1 ) #30 Brake = ~Brake; for( i=0; i<6; i=i+1 ) #30 Acc = ~Acc; for( i=0; i<4; i=i+1 ) #30 Brake = ~Brake; end initial $monitor(Clock, Rst, Brake, Acc, Speed ); endmodule


Bloger: moltak.net